1. Field of the Invention
The present invention relates to a data processor with cache memories, and more particularly, to a data processor which is advantageous to a real-time multi-tasking system with plural cache memories.
2. Description of Related Art
FIG. 1 is a block diagram showing a configuration of the main portion of a conventional data processor with a cache memory by way of example, whose configuration is essentially the same as that in such as Japanese Patent Application No. 63-11222 (1988).
In the figure a reference numeral 1 designates a data processing unit which accesses data to a cache memory 2 or a main memory 3 which will be described later.
Both the cache memory 2 and the data processing unit 1 are connected through a data bus DB to a system bus SB, and a bus driver 4 is provided between the system bus SB and both the data processing unit 1 and cache memory 2.
The bus driver 4 is enabled or disabled by controlling of a gate circuit 41 with an output signal of an AND gate 42, so that driving of the data bus DB is controlled. Accordingly, the data processing unit 1 and cache memory 2 are disconnected or connected to the system bus SB.
The AND gate 42 of the bus driver 4 receives two inputs, one of which is a first signal S1 output from the cache memory 2 and the other of which is a second signal S2 output from the data processing unit 1, respectively.
The system bus SB is connected to the data bus DB, the main memory 3, and other peripheral devices, respectively.
The main memory 3 stores various kinds of data to be accessed by the data processing unit 1.
The cache memory 2 as employs 4-way set-associative and data-writing-through, so that the data processor can maintain cache data to be identical with that of the main memory 3 at all times.
Functional operation of such a conventional data processor with a cache memory as referred to above will be described below.
When the data processing unit 1 executes read-access of the required data, the cache memory 2 judges whether the data to be accessed is stored therein or not. Where the data to be accessed is stored in the cache memory 2, which is called "cache-hit", the data to be accessed is delivered from the cache memory 2 through the data bus DB to the data processing unit 1. On the other hand, where the data to be accessed is not stored in the cache memory 2, which is called "cache-miss", 4-word data (corresponding to the number of lines of the cache memory 2) including the data to be accessed is delivered from the main memory 3 through the system bus SB and the data bus DB to the cache memory 2 and the data processing unit 1, respectively, following which the cache memory 2 acquiring and holds the 4-word data delivered from the main memory 3, while the data processing unit 1 fetches the data to be accessed, respectively.
The 4-way set-associative cache memory 2 is adapted to be capable of setting the accessing type of the data held therein by the two way unit, where the "accessing type" designates that the data being accessed in its bus cycle is one out of an instruction, an operand data, a command to the data processor and the like. In the cycle which the data processing unit 1 executes a read access or write-access of the required data, information on the accessing type of data corresponding to its address is output from the data processing unit 1. In the case of a cache-miss when the data processing unit 1 executes read access of the data, the cache memory 2 stores data in accordance with the information of the accessing type of the corresponding data outputted from the data processing unit 1. In addition, where the data processing unit 1 executes read access or write access of the required data, the cache memory 2 refers to the information on the accessing type of corresponding data outputted from the data processing unit 1.
When executing read or write access of the data, the data processing unit 1 first accesses to the cache memory 2. At that time, a signal output from the data processing unit 1 is directly given to the main memory 3 and, when the cache memory 2 is in the cache-hit condition, the data output from the cache memory 2 to the data processing unit 1 collides with the data output from the main memory 3 to the data processing unit 1 on the data bus DB. To avoid this collision, the bus driver 4 is provided between the data bus DB and the system bus SB so that the output signal for accessing data from data processing unit 1 or the input signal from the system bus SB to the data processing unit 1 can be disconnected.
Where the data processing unit 1 meets the cache-miss condition, there is a need to transfer the data stored in the main memory 3 to the data processing unit 1. Accordingly, the cache memory 2 allows the signal showing that it has been in the cache-miss condition, that is, the first signal S1, to become active and sends it to the AND gate 42 of the bus driver 4 as a first input thereof. As a result, the gate circuit 41 of the bus driver 4 is opened so as to drive the data bus DB, which makes it possible to transmit/receive data between the data processing unit 1 and the main memory 3.
Further, where the data processing unit 1 accesses to an area such as I/O area whose data must not be cache, that is, whose data must not be held in the cache memory 2, the processing unit 1 outputs a non-cachable signal, that is, a second signal S2. Since this second signal S2 is given as the second input of the AND gate 42 of bus driver 4, the bus driver 4 drives the data bus DB so that data can be transmitted/received between the data processing unit 1 and the main memory 3.
As may be seen from the above description, excepting the case where the cache memory 2 is in the cache-hit condition, it is necessary that the first signal S1 or the second signal S2 should be sent to the bus driver 4 so as to enable the gate circuit 41 and drive the data bus DB.
In order to activate the cache memory 2, there is a need to set a predetermined value in an internal register of the cache memory 2. By setting a CE bit (Cache Enable Bit) of the internal register (not shown) in the cache memory 2 to be "1", the cache memory 2 is activated so that it can execute caching.
Where the environment of peripheral devices is established by the time that the cache memory 2 starts to be activated after such a data processor as shown in FIG. 1 has been activated, neither the first signal S1 nor the second signal S2 are active, the data bus DB cannot, is not liable to be driven by the bus driver 4. In other words, because such a condition as that data can not be transmitted/received between the data processing unit 1 and the main memory 3 and peripheral devices 5 is maintained until the cache memory 2 starts to be activated, the environment of peripheral devices 5 is not be established.
The conventional data processor is thus problematic in that a peripheral device connected to the system bus cannot be initialized without the data processor issuing a separate signal. Otherwise, the driver is not connected to the system bus until after the cache memory is activated.
FIG. 2 is a block diagram of such a data processor using a multi-cache system with both a first cache memory 21 and a second cache memory 22.
In this data processor, both a first signal S11 of the first cache memory 21 and a first signal S12 of the second cache memory 22 are inputs of an OR gate 43, whose output signal is to the first input of the AND gate 42 of the bus driver 4.
Further in this data processor shown in FIG. 2, during the period that the second cache memory 22 has not been and activated the first cache memory 21 has already been activated, only both cases where the first signal S11 has been output in the cache-miss condition of the first cache memory 21 and where the data processing unit 1 has accessed the non-cachable area and the second signal S2 has been output will the bus drive 4 drives the data bus DB.
Assuming that the first cache memory 21 and the second cache memory 22 support different accessing types of data, respectively, during such period that the first cache memory 21 is still not activated as described above, where the environment of the peripheral devices 5 is established when the whole data processor is activated, and when the data processing unit 1 accesses the data of accessing type supported by the second cache memory 22, neither the first cache memory 21 nor the second cache memory 22 outputs the first signal S1, that is, the first signals S11 and S12, nor does the data processing unit 1 the second signal S2. Consequently, the bus driver 4 is unable to drive the data bus DB so that data can be transmitted/received between the peripheral devices 5 and the data processing unit 1, which makes it impossible to establish the environment of the peripheral devices 5.
As may be seen from the above description, in the conventional data processor with plural cache memories, data can not be transmitted/received between the data processing unit 1 and the peripheral devices 5 until the time that the cache memory starts to be activated after the whole data processor has been activated, which results in a disadvantage that the environment of the peripheral devices can not be established.